/* Copyright (c) 2025 Beijing Semidrive Technology Corporation
 * SPDX-License-Identifier: Apache-2.0
 *
 * Licensed under the Apache License, Version 2.0 (the "License");
 * you may not use this file except in compliance with the License.
 * You may obtain a copy of the License at
 *
 * http://www.apache.org/licenses/LICENSE-2.0
 *
 * Unless required by applicable law or agreed to in writing, software
 * distributed under the License is distributed on an "AS IS" BASIS,
 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
 * See the License for the specific language governing permissions and
 * limitations under the License.
 */
/** *****************************************************************************************************
 * \file     Mcu_Cfg.c                                                                                  *
 * \brief    AUTOSAR 4.3.1 MCAL MCU Driver                                                              *
 *                                                                                                      *
 * <table>                                                                                              *
 * <tr><th>Date           <th>Version                                                                   *
 * <tr><td>2025-03-25 19:03:22     <td>1.0.0                                                                *
 * </table>                                                                                             *
 *******************************************************************************************************/

#ifdef __cplusplus
extern "C" {
#endif
/********************************************************************************************************
 *                                      Include header files                                            *
 *******************************************************************************************************/
#include "Mcu.h"
#include "Mcu_Cfg.h"
#include "Mcu_ClkCfgNode.h"
#include "Mcu_ResetSig.h"

#define MCU_START_SEC_CONST_UNSPECIFIED
#include "Mcu_MemMap.h"
/* PRQA S 2840 EOF */



#if (MCU_NO_PLL == STD_OFF)
static const Mcu_ClkPllConfigType Mcu_ClkPllConfig = {
    .configNum = 9,

    .configNodes[0].clkNode = CLK_NODE(g_pll1_vco),

#ifdef MCU_pll1_DSM_EN
    .configNodes[0].spreadConfig = &Mcu_pll1SpreadConfigs,
#endif

    .configNodes[1].clkNode = CLK_NODE(g_pll1_pll_ck0),

    .configNodes[2].clkNode = CLK_NODE(g_pll1_pll_ck1),
#if (STD_ON == MCU_SF_CLK_ND_CFG)
    .configNodes[0].rate = 1600000000U,
    .configNodes[1].rate = 400000000U,
    .configNodes[2].rate = 400000000U,
#else /* OD CFG */
    .configNodes[0].rate = 2400000000U,
    .configNodes[1].rate = 400000000U,
    .configNodes[2].rate = 600000000U,
#endif /* STD_ON == MCU_SF_CLK_ND_CFG */

    .configNodes[3].clkNode = CLK_NODE(g_pll2_vco),
    .configNodes[3].rate = 2000000000U,
#ifdef MCU_pll2_DSM_EN
    .configNodes[3].spreadConfig = &Mcu_pll2SpreadConfigs,
#endif

    .configNodes[4].clkNode = CLK_NODE(g_pll2_pll_ck0),
    .configNodes[4].rate = 500000000U,

    .configNodes[5].clkNode = CLK_NODE(g_pll2_pll_ck1),
    .configNodes[5].rate = 500000000U,

    .configNodes[6].clkNode = CLK_NODE(g_pll3_vco),
    .configNodes[6].rate = 2400000000U,
#ifdef MCU_pll3_DSM_EN
    .configNodes[6].spreadConfig = &Mcu_pll3SpreadConfigs,
#endif

    .configNodes[7].clkNode = CLK_NODE(g_pll3_pll_ck0),
    .configNodes[7].rate = 600000000U,

    .configNodes[8].clkNode = CLK_NODE(g_pll3_pll_ck1),
    .configNodes[8].rate = 400000000U,
};

static const Mcu_ClkBusConfigType Mcu_ClkBusConfig = {
    .configNum = 2,
    .configNodes[0].clkNode = CLK_NODE(g_ckgen_bus_cr5_se_seip_r52),
#if (STD_ON == MCU_SF_CLK_ND_CFG)
#if (STD_OFF == MCU_CR52_FREQUENCY_HALVED)
    .configNodes[0].rate = 500000000U,
    .configNodes[0].postDiv = CKGEN_BUS_DIV_4_2_1,
#else
    .configNodes[0].rate = 250000000U,
    .configNodes[0].postDiv = CKGEN_BUS_DIV_2_2_1,
#endif
#else /* OD cfg */
#if (STD_OFF == MCU_CR52_FREQUENCY_HALVED)
    .configNodes[0].rate = 600000000U,
    .configNodes[0].postDiv = CKGEN_BUS_DIV_4_2_1,
#else
    .configNodes[0].rate = 300000000U,
    .configNodes[0].postDiv = CKGEN_BUS_DIV_2_2_1,
#endif
#endif /* STD_ON == MCU_SF_CLK_ND_CFG */

    .configNodes[1].clkNode = CLK_NODE(g_ckgen_bus_cr5_lp),
    .configNodes[1].rate = 200000000U,
    .configNodes[1].postDiv = CKGEN_BUS_DIV_2_2_1,
};
#endif /* (MCU_NO_PLL == STD_OFF) */

static const Mcu_ClkIpConfigType Mcu_ClkIpConfig = {
    .configNodes[0].clkNode = CLK_NODE(g_ckgen_ip_i2c2_4),
    .configNodes[0].rate = 133330000U,
    .configNodes[1].clkNode = CLK_NODE(g_ckgen_ip_spi3_14),
    .configNodes[1].rate = 100000000U,
    .configNodes[2].clkNode = CLK_NODE(g_ckgen_ip_uart3_20),
    .configNodes[2].rate = 83330000U,
    .configNodes[3].clkNode = CLK_NODE(g_ckgen_ip_sent),
    .configNodes[3].rate = 100000000U,
    .configNodes[4].clkNode = CLK_NODE(g_ckgen_ip_enet1_tx),
    .configNodes[4].rate = 250000000U,
    .configNodes[5].clkNode = CLK_NODE(g_ckgen_ip_enet1_rmii),
    .configNodes[5].rate = 50000000U,
    .configNodes[6].clkNode = CLK_NODE(g_ckgen_ip_enet1_phy_ref),
    .configNodes[6].rate = 125000000U,
    .configNodes[7].clkNode = CLK_NODE(g_ckgen_ip_enet_timer_sec),
    .configNodes[7].rate = 250000000U,
    .configNodes[8].clkNode = CLK_NODE(g_ckgen_ip_enet2_tx),
    .configNodes[8].rate = 250000000U,
    .configNodes[9].clkNode = CLK_NODE(g_ckgen_ip_enet2_rmii),
    .configNodes[9].rate = 50000000U,
    .configNodes[10].clkNode = CLK_NODE(g_ckgen_ip_enet2_phy_ref),
    .configNodes[10].rate = 125000000U,
    .configNodes[11].clkNode = CLK_NODE(g_ckgen_ip_xspi1a),
    .configNodes[11].rate = 300000000U,
    .configNodes[12].clkNode = CLK_NODE(g_ckgen_ip_xspi1b),
    .configNodes[12].rate = 300000000U,
    .configNodes[13].clkNode = CLK_NODE(g_ckgen_ip_xtrg1),
    .configNodes[13].rate = 200000000U,
    .configNodes[14].clkNode = CLK_NODE(g_ckgen_ip_xtrg2),
    .configNodes[14].rate = 200000000U,
    .configNodes[15].clkNode = CLK_NODE(g_ckgen_ip_sehc1),
    .configNodes[15].rate = 300000000U,
    .configNodes[16].clkNode = CLK_NODE(g_ckgen_ip_etmr1),
    .configNodes[16].rate = 200000000U,
    .configNodes[17].clkNode = CLK_NODE(g_ckgen_ip_etmr2),
    .configNodes[17].rate = 200000000U,
    .configNodes[18].clkNode = CLK_NODE(g_ckgen_ip_etmr3),
    .configNodes[18].rate = 200000000U,
    .configNodes[19].clkNode = CLK_NODE(g_ckgen_ip_etmr4),
    .configNodes[19].rate = 200000000U,
    .configNodes[20].clkNode = CLK_NODE(g_ckgen_ip_saci_clk),
    .configNodes[20].rate = 200000000U,
    .configNodes[21].clkNode = CLK_NODE(g_ckgen_ip_saci_pdm_clk),
    .configNodes[21].rate = 200000000U,
    .configNodes[22].clkNode = CLK_NODE(g_ckgen_ip_epwm1),
    .configNodes[22].rate = 200000000U,
    .configNodes[23].clkNode = CLK_NODE(g_ckgen_ip_epwm2),
    .configNodes[23].rate = 200000000U,
    .configNodes[24].clkNode = CLK_NODE(g_ckgen_ip_epwm3),
    .configNodes[24].rate = 200000000U,
    .configNodes[25].clkNode = CLK_NODE(g_ckgen_ip_epwm4),
    .configNodes[25].rate = 200000000U,
    .configNodes[26].clkNode = CLK_NODE(g_ckgen_ip_can3_16),
    .configNodes[26].rate = 80000000U,
    .configNodes[27].clkNode = CLK_NODE(g_ckgen_ip_sadc1),
    .configNodes[27].rate = 166670000U,
    .configNodes[28].clkNode = CLK_NODE(g_ckgen_ip_sadc2),
    .configNodes[28].rate = 166670000U,
    .configNodes[29].clkNode = CLK_NODE(g_ckgen_ip_sadc3),
    .configNodes[29].rate = 166670000U,
    .configNodes[30].clkNode = CLK_NODE(g_ckgen_ip_sadc4),
    .configNodes[30].rate = 166670000U,
    .configNodes[31].clkNode = CLK_NODE(g_ckgen_ip_sadc5),
    .configNodes[31].rate = 166670000U,
    .configNodes[32].clkNode = CLK_NODE(g_ckgen_ip_sadc6),
    .configNodes[32].rate = 166670000U,
    .configNodes[33].clkNode = CLK_NODE(g_ckgen_ip_sys_cnt),
    .configNodes[33].rate = 24000000U,
    .configNodes[34].clkNode = CLK_NODE(g_ckgen_ip_pt_sns_sf),
    .configNodes[34].rate = 100000U,
    .configNodes[35].clkNode = CLK_NODE(g_ckgen_ip_i2s_mclk),
    .configNodes[35].rate = 133330000U,
    .configNodes[36].clkNode = CLK_NODE(g_ckgen_ip_trace),
    .configNodes[36].rate = 66670000U,
    .configNodes[37].clkNode = CLK_NODE(g_ckgen_ip_ioc),
    .configNodes[37].rate = 200000000U,
    .configNodes[38].clkNode = CLK_NODE(g_ckgen_ip_i2c1),
    .configNodes[38].rate = 133330000U,
    .configNodes[39].clkNode = CLK_NODE(g_ckgen_ip_spi1_2),
    .configNodes[39].rate = 100000000U,
    .configNodes[40].clkNode = CLK_NODE(g_ckgen_ip_can1_2),
    .configNodes[40].rate = 80000000U,
    .configNodes[41].clkNode = CLK_NODE(g_ckgen_ip_sadc7),
    .configNodes[41].rate = 166670000U,
    .configNodes[42].clkNode = CLK_NODE(g_ckgen_ip_uart1_2),
    .configNodes[42].rate = 83330000U,
    .configNum = 43U,
};

/* Set pll(only IRAM BUILD mode), bus and ip slice frequency.
   Pll and bus frequency is fixed, ip frequency is configurable. */
static const Mcu_ClkConfigType Mcu_ClkPrepareConfig = {
#if (MCU_NO_PLL == STD_OFF)
    .clkPllConfig = &Mcu_ClkPllConfig,
    .clkBusConfig = &Mcu_ClkBusConfig,
#else
    .clkPllConfig = NULL_PTR,
    .clkBusConfig = NULL_PTR,
#endif /* (MCU_NO_PLL == STD_OFF) */
    .clkIpConfig = &Mcu_ClkIpConfig,
};

/* enable SF/LP gate used */
static const Mcu_ClkCgConfigType Mcu_ClkEnableConfig = {
    .configNodes[0] = {&g_ckgen_i2c2[0]},
    .configNodes[1] = {&g_ckgen_i2c3[0]},
    .configNodes[2] = {&g_ckgen_i2c4[0]},
    .configNodes[3] = {&g_ckgen_spi3[0]},
    .configNodes[4] = {&g_ckgen_spi4[0]},
    .configNodes[5] = {&g_ckgen_spi5[0]},
    .configNodes[6] = {&g_ckgen_spi6[0]},
    .configNodes[7] = {&g_ckgen_spi7[0]},
    .configNodes[8] = {&g_ckgen_spi8[0]},
    .configNodes[9] = {&g_ckgen_spi9[0]},
    .configNodes[10] = {&g_ckgen_spi10[0]},
    .configNodes[11] = {&g_ckgen_spi11[0]},
    .configNodes[12] = {&g_ckgen_spi12[0]},
    .configNodes[13] = {&g_ckgen_spi13[0]},
    .configNodes[14] = {&g_ckgen_spi14[0]},
    .configNodes[15] = {&g_ckgen_uart3[0]},
    .configNodes[16] = {&g_ckgen_uart4[0]},
    .configNodes[17] = {&g_ckgen_uart5[0]},
    .configNodes[18] = {&g_ckgen_uart6[0]},
    .configNodes[19] = {&g_ckgen_uart7[0]},
    .configNodes[20] = {&g_ckgen_uart8[0]},
    .configNodes[21] = {&g_ckgen_uart9[0]},
    .configNodes[22] = {&g_ckgen_uart10[0]},
    .configNodes[23] = {&g_ckgen_uart11[0]},
    .configNodes[24] = {&g_ckgen_uart12[0]},
    .configNodes[25] = {&g_ckgen_uart13[0]},
    .configNodes[26] = {&g_ckgen_uart14[0]},
    .configNodes[27] = {&g_ckgen_uart15[0]},
    .configNodes[28] = {&g_ckgen_uart16[0]},
    .configNodes[29] = {&g_ckgen_uart17[0]},
    .configNodes[30] = {&g_ckgen_uart18[0]},
    .configNodes[31] = {&g_ckgen_uart19[0]},
    .configNodes[32] = {&g_ckgen_uart20[0]},
    .configNodes[33] = {&g_ckgen_sent[0]},
    .configNodes[34] = {&g_ckgen_enet1[0]},
    .configNodes[35] = {&g_ckgen_enet2[0]},
    .configNodes[36] = {&g_ckgen_xspi1a[0]},
    .configNodes[37] = {&g_ckgen_xspi1b[0]},
    .configNodes[38] = {&g_ckgen_xtrg1[0]},
    .configNodes[39] = {&g_ckgen_xtrg2[0]},
    .configNodes[40] = {&g_ckgen_sehc1[0]},
    .configNodes[41] = {&g_ckgen_etmr1[0]},
    .configNodes[42] = {&g_ckgen_etmr2[0]},
    .configNodes[43] = {&g_ckgen_etmr3[0]},
    .configNodes[44] = {&g_ckgen_etmr4[0]},
    .configNodes[45] = {&g_ckgen_saci1[0]},
    .configNodes[46] = {&g_ckgen_epwm1[0]},
    .configNodes[47] = {&g_ckgen_epwm2[0]},
    .configNodes[48] = {&g_ckgen_epwm3[0]},
    .configNodes[49] = {&g_ckgen_epwm4[0]},
    .configNodes[50] = {&g_ckgen_canfd3[0]},
    .configNodes[51] = {&g_ckgen_canfd4[0]},
    .configNodes[52] = {&g_ckgen_canfd5[0]},
    .configNodes[53] = {&g_ckgen_canfd6[0]},
    .configNodes[54] = {&g_ckgen_canfd7[0]},
    .configNodes[55] = {&g_ckgen_canfd8[0]},
    .configNodes[56] = {&g_ckgen_canfd9[0]},
    .configNodes[57] = {&g_ckgen_canfd10[0]},
    .configNodes[58] = {&g_ckgen_canfd11[0]},
    .configNodes[59] = {&g_ckgen_canfd12[0]},
    .configNodes[60] = {&g_ckgen_canfd13[0]},
    .configNodes[61] = {&g_ckgen_canfd14[0]},
    .configNodes[62] = {&g_ckgen_canfd15[0]},
    .configNodes[63] = {&g_ckgen_canfd16[0]},
    .configNodes[64] = {&g_ckgen_adc1[0]},
    .configNodes[65] = {&g_ckgen_adc2[0]},
    .configNodes[66] = {&g_ckgen_adc3[0]},
    .configNodes[67] = {&g_ckgen_adc4[0]},
    .configNodes[68] = {&g_ckgen_adc5[0]},
    .configNodes[69] = {&g_ckgen_adc6[0]},
    .configNodes[70] = {&g_ckgen_sys_cnt[0]},
    .configNodes[71] = {&g_ckgen_pt_sns_sf[0]},
    .configNodes[72] = {&g_ckgen_cssys[0]},
    .configNodes[73] = {&g_ckgen_ioc[0]},
    .configNodes[74] = {&g_ckgen_i2c1[0]},
    .configNodes[75] = {&g_ckgen_spi1[0]},
    .configNodes[76] = {&g_ckgen_spi2[0]},
    .configNodes[77] = {&g_ckgen_canfd1[0]},
    .configNodes[78] = {&g_ckgen_canfd2[0]},
    .configNodes[79] = {&g_ckgen_adc7[0]},
    .configNodes[80] = {&g_ckgen_dma_sf1_rst0[0]},
    .configNodes[81] = {&g_ckgen_dma_sf1_rst1[0]},
    .configNodes[82] = {&g_ckgen_dma_sf2_rst0[0]},
    .configNodes[83] = {&g_ckgen_dma_sf2_rst1[0]},
    .configNodes[84] = {&g_ckgen_mb[0]},
    .configNodes[85] = {&g_ckgen_dpe[0]},
    .configNodes[86] = {&g_ckgen_uart2[0]},
    .configNum = 87U,
};

/* disable SF gate not used, do not disable LP gate not used */
static const Mcu_ClkCgConfigType Mcu_ClkDisableConfig = {
    .configNum = 0U,
};

/* reset SF/LP signal used */
static const Mcu_ResetConfigType Mcu_DeassertConfig = {
    .configNodes[0] = &rstsig_i2c2,
    .configNodes[1] = &rstsig_i2c3,
    .configNodes[2] = &rstsig_i2c4,
    .configNodes[3] = &rstsig_spi3,
    .configNodes[4] = &rstsig_spi4,
    .configNodes[5] = &rstsig_spi5,
    .configNodes[6] = &rstsig_spi6,
    .configNodes[7] = &rstsig_spi7,
    .configNodes[8] = &rstsig_spi8,
    .configNodes[9] = &rstsig_spi9,
    .configNodes[10] = &rstsig_spi10,
    .configNodes[11] = &rstsig_spi11,
    .configNodes[12] = &rstsig_spi12,
    .configNodes[13] = &rstsig_spi13,
    .configNodes[14] = &rstsig_spi14,
    .configNodes[15] = &rstsig_uart3,
    .configNodes[16] = &rstsig_uart4,
    .configNodes[17] = &rstsig_uart5,
    .configNodes[18] = &rstsig_uart6,
    .configNodes[19] = &rstsig_uart7,
    .configNodes[20] = &rstsig_uart8,
    .configNodes[21] = &rstsig_uart9,
    .configNodes[22] = &rstsig_uart10,
    .configNodes[23] = &rstsig_uart11,
    .configNodes[24] = &rstsig_uart12,
    .configNodes[25] = &rstsig_uart13,
    .configNodes[26] = &rstsig_uart14,
    .configNodes[27] = &rstsig_uart15,
    .configNodes[28] = &rstsig_uart16,
    .configNodes[29] = &rstsig_uart17,
    .configNodes[30] = &rstsig_uart18,
    .configNodes[31] = &rstsig_uart19,
    .configNodes[32] = &rstsig_uart20,
    .configNodes[33] = &rstsig_sent,
    .configNodes[34] = &rstsig_enet1,
    .configNodes[35] = &rstsig_enet2,
    .configNodes[36] = &rstsig_xspi1a,
    .configNodes[37] = &rstsig_xspi1b,
    .configNodes[38] = &rstsig_xtrg1,
    .configNodes[39] = &rstsig_xtrg2,
    .configNodes[40] = &rstsig_sehc1,
    .configNodes[41] = &rstsig_etmr1,
    .configNodes[42] = &rstsig_etmr2,
    .configNodes[43] = &rstsig_etmr3,
    .configNodes[44] = &rstsig_etmr4,
    .configNodes[45] = &rstsig_saci1,
    .configNodes[46] = &rstsig_epwm1,
    .configNodes[47] = &rstsig_epwm2,
    .configNodes[48] = &rstsig_epwm3,
    .configNodes[49] = &rstsig_epwm4,
    .configNodes[50] = &rstsig_canfd3,
    .configNodes[51] = &rstsig_canfd4,
    .configNodes[52] = &rstsig_canfd5,
    .configNodes[53] = &rstsig_canfd6,
    .configNodes[54] = &rstsig_canfd7,
    .configNodes[55] = &rstsig_canfd8,
    .configNodes[56] = &rstsig_canfd9,
    .configNodes[57] = &rstsig_canfd10,
    .configNodes[58] = &rstsig_canfd11,
    .configNodes[59] = &rstsig_canfd12,
    .configNodes[60] = &rstsig_canfd13,
    .configNodes[61] = &rstsig_canfd14,
    .configNodes[62] = &rstsig_canfd15,
    .configNodes[63] = &rstsig_canfd16,
    .configNodes[64] = &rstsig_adc1,
    .configNodes[65] = &rstsig_adc2,
    .configNodes[66] = &rstsig_adc3,
    .configNodes[67] = &rstsig_adc4,
    .configNodes[68] = &rstsig_adc5,
    .configNodes[69] = &rstsig_adc6,
    .configNodes[70] = &rstsig_ioc,
    .configNodes[71] = &rstsig_i2c1,
    .configNodes[72] = &rstsig_spi1,
    .configNodes[73] = &rstsig_spi2,
    .configNodes[74] = &rstsig_canfd1,
    .configNodes[75] = &rstsig_canfd2,
    .configNodes[76] = &rstsig_adc7,
    .configNodes[77] = &rstsig_dma_sf1_rst0,
    .configNodes[78] = &rstsig_dma_sf1_rst1,
    .configNodes[79] = &rstsig_dma_sf2_rst0,
    .configNodes[80] = &rstsig_dma_sf2_rst1,
    .configNodes[81] = &rstsig_mb,
    .configNodes[82] = &rstsig_dpe,
    .configNodes[83] = &rstsig_uart2,
    .configNum = 84U,
};

/* assert SF signal not used, do not assert LP signal not used*/
static const Mcu_ResetConfigType Mcu_AssertConfig = {
    .configNum = 0U,
};


/* PRQA S 0703 13 */
static const Mcu_ClockConfigType Mcu_ClockCfg[MCU_MAX_CLKCFGS] = {
    {
        &Mcu_ClkPrepareConfig,
        &Mcu_ClkEnableConfig,
        &Mcu_ClkDisableConfig,
        &Mcu_DeassertConfig,
        &Mcu_AssertConfig,
    },
};

const Mcu_ConfigType Mcu_Cfg = {

    .numRamSections     = (Mcu_RamSectionType)0U,  /* numRamSections */
    .numClkCfgs         = (Mcu_ClockType)1U,  /* numClkCfgs */
    .ramCfgsPtr         = NULL_PTR,
    .clkCfgsPtr         = &Mcu_ClockCfg,
};

#define MCU_STOP_SEC_CONST_UNSPECIFIED

#include "Mcu_MemMap.h"

#ifdef __cplusplus
};
#endif
/* End of file */
